This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-023973, filed Jan. 31, 2001; and No. 2001-085821, filed Mar. 23, 2001, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a selection gate transistor in a memory cell portion which is, for example, applied to a NAND type flash memory.
2. Description of the Related Art
FIG. 57 shows a sectional view of memory cell transistors and selection gate transistors taken in a gate length xe2x80x9cLxe2x80x9d direction in a conventional NAND type semiconductor memory device.
A contact hole 34 is formed between the gate electrodes of the selection gate transistors in self-alignment with respect to these gate electrodes. A TEOS film 29 is deposited on the gate sidewalls of the memory cell transistors to improve hot carrier characteristics.
On the other hand, the selection gate transistors are arranged such that the TEOS film 29 of the gate sidewalls thereof is removed before the contact hole 34 is opened to prevent the short-circuit between a contact filling material and the gate electrodes because the TEOS film 29 is etched when the contact hole 34 is opened. Since an impurity is simultaneously ion-implanted in the channel regions and source/drain diffusion layer regions 28 of the memory cell transistors and the selection gate transistors, the impurity distribution in the channel regions and the source/drain diffusion layer regions 28 is similar in the memory cell transistors and the selection gate transistors.
In the NAND type semiconductor memory device, when data xe2x80x9c1xe2x80x9d is written to a memory cell (i.e. when electrons are not implanted in floating gates and a threshold value in erasing is maintained), the electrons are prevented from being implanted in the floating gates 5 and 11 by charging an initial potential from a bit line through the selection gate transistor connected to the memory cell transistor, applying a writing voltage to a selected word line and applying a transfer voltage to non-selected word lines, and increasing the potential of the channel region of the memory cell transistor making use of capacitance coupling. As a result, the capacitance of the channel region is reduced by decreasing the concentration of the impurity therein so that the potential of the channel region is liable to increase, which improves data xe2x80x9c1xe2x80x9d writing characteristics.
However, there are such circumstances that the non-volatile semiconductor memory device cannot be normally operated by a decrease in the threshold voltage of the selection gate transistors and an increase in the off-leak current thereof which are caused when the concentration of the impurity in the channel regions is reduced. This is because that the distribution of the impurity in the channel regions of the memory cell transistors is the same as that of the impurity in the channel regions of the selection gate transistors.
FIG. 58 shows a sectional view of a part of manufacturing processes of a memory cell and a selection gate transistor of a conventional NAND type flash memory taken along the gate length direction thereof.
In the figure, reference numeral 1 denotes a silicon substrate and reference numeral 3 denotes a well/channel region. The memory cell and selection gate transistor are simultaneously subjected to impurity ion implantation into the well/channel region 3 and formation of a gate insulation film 4.
The memory cell of the NAND memory cell unit has a gate structure where a charge accumulation layer (floating gate) and a control gate layer are stacked one atop the other via an ONO film 13 on a substrate. The floating gate comprises a first layer of polysilicon 5 and a second layer as a floating gate 11 which are deposited in layers. The control gate layer 14 is formed of a polysilicon/WSi laminated film. Here, indicated by reference numeral 15 is a silicon nitride film and 20 is a silicon oxide film. Gate electrodes of the selection gate transistor are designated by reference numerals 5 and 11. Reference numeral 28 denotes a source/drain diffusion layer of the memory cell and selection gate transistor. A contact hole is to be formed between the gate electrodes of the selection gate transistor.
Impurity ion implantation for forming the source/drain diffusion layer 28 of the memory cell and selection gate transistor is carried out simultaneously, and the source/drain diffusion layer 28 of the selection gate transistor is connected to the memory cell unit at one end and is electrically connected to a bit line or source line through the contact hole at the other end.
FIG. 59 shows a concentration distribution of a p-type impurity in a substrate depth direction at a channel region of the selection gate transistor along the line C-Cxe2x80x2 shown in FIG. 58 and a concentration distribution of a p-type impurity in the substrate depth direction at a channel region of the memory cell along the line D-Dxe2x80x2 shown in FIG. 58.
As mentioned above, since an impurity is implanted simultaneously into the channel regions of the memory cell and selection gate transistor, the impurity distributions of the both channel regions become the same as shown in FIG. 59.
It is known that a NAND type flash memory is adapted to prevent the data of an unselected block being read out at a time of data reading by turning off the selection gate transistor. For this purpose, in order to allow a threshold voltage of the selection gate transistor to satisfy the limitations of the cut-off characteristics, it is necessary to control the impurity concentrations in the channel regions.
The NAND type flash memory, on the other hand, is adapted to prevent electrons to be introduced into the floating gates 5 and 11 when xe2x80x9c1xe2x80x9d data is written to the memory cell (i.e. when a threshold value during an erased state is maintained without implanting electrons into the floating gate), by charging the memory cell to the initial potential through the bit line via the selection gate transistor connected to the memory cell, applying a write voltage and a transfer voltage to a selected word line and an unselected word line, respectively, and rising the potential of the channel region of the memory cell by means of capacitive coupling. Thus, decreasing each impurity concentrations of the respective channel regions reduces the channel capacity, which facilitates a rise in potential in the channel region and improves the xe2x80x9c1xe2x80x9d data writing efficiency.
Conventionally, however, since the impurity distributions of the channel regions of the memory cell and selection gate transistor are the same as stated above, when decreasing the impurity distribution in the channel regions in order to improve the xe2x80x9c1xe2x80x9d data writing efficiency as mentioned before, a trade-off relationship arises in which the threshold voltage of the selection gate transistor decreases and an off-leak current increases.
According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer; and
a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit,
wherein the shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer; and
a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit,
wherein the channel region between the source diffusion layer region of the selection gate transistor and the drain diffusion layer region thererof includes a region having a different concentration of impurity at the positions thereof which have the same depth from the boundary between the semiconductor substrate and a gate insulation film.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of forming a mask having an aperture on the side of the gate electrode of the selection gate transistor opposite to the side thereof facing the memory cell transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the aperture of the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of forming a first insulation film on the sidewalls of the gate electrodes of the memory cell transistor and the selection gate transistor;
a step of forming a second insulation film on the first insulation film;
a step of forming a mask having an aperture on the side of the gate electrode of the selection gate transistor opposite to the side thereof facing the memory cell transistor;
a step of removing the second insulation film through the aperture of the mask; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the aperture of the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and a selection gate transistor having a first conductive type channel region on a semiconductor substrate;
a step of opening a contact hole through the source/drain diffusion layer region of the selection gate transistor in self-alignment with respect to the gate electrode of the selection gate transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate through the contact hole.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
a step of forming gate electrodes of a memory cell transistor and selection gate transistors having a first conductive type channel region on a semiconductor substrate in such a manner that the space between the gate electrodes of the selection gate transistors is set larger than the space between the gate electrode of the memory cell transistor and the gate electrode of a selection gate transistor; and
a step of implanting a first conductive type impurity in the semiconductor substrate at such an angle that the impurity is not implanted between the gate electrode of the memory cell transistor and the gate electrode of the selection gate transistor and is implanted between the gate electrodes of the selection gate transistors.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through the gate insulation film and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors include a pair of first selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the channel regions of the pair of selection gate transistors have the same impurity concentration in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the concentration distribution of impurity in the channel regions of the pair of selection gate transistors is different from that of the channel region of the memory cell.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film formed of the same layer as the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of first selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the effective impurity concentration of the source/drain diffusion layer of the pair of first selection gate transistors is lower than that of the source/drain diffusion layer of the memory cell at a depth equal from the boundary between the semiconductor substrate and the gate insulation film.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistors each having a gate electrode formed through a gate insulation film formed of the same layer as the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have first selection gate transistors and second selection gate transistors disposed in confrontation with each other through a contact portion connected to the bit line or the source line, and the structure of the first selection gate transistors is substantially different from that of the second selection gate transistors;
the channel regions of the first selection gate transistors have the same impurity concentration in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the concentration distribution of impurity of the channel regions of the first selection gate transistors is different from that of the channel region of the memory cell; and
each of the second selection gate transistors has a portion in which the impurity concentration of the channel region thereof is different in a gate length direction at the above depth from the boundary between the semiconductor substrate, and the impurity concentration of the portion of the channel region containing a high concentration impurity is the same as that of the channel region of each of the first selection gate transistors at the above depth from the boundary between the semiconductor substrate and the gate insulation film.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have first selection gate transistors and second selection gate transistors disposed in confrontation with each other through a contact portion connected to the bit line or the source line, and the structure of the first selection gate transistors is substantially different from that of the second selection gate transistors;
the impurity concentration of the source diffusion layer of each of the first selection gate transistors is the same as that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the effective impurity concentration of the source/drain diffusion layer of each of the first selection gate transistors is lower than that of the source/drain diffusion layer of the memory cell; and
the impurity concentration of the source diffusion layer of each of the second selection gate transistors is different from that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the impurity concentration of the source diffusion layer or the drain diffusion layer, which is connected to the bit line or the source line, of each of the second selection gate transistors is the same as that of the source/drain diffusion layer of each of the first selection gate transistors.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell having a laminated gate structure of a charge accumulation layer and a control gate layer formed on a semiconductor substrate through a gate insulation film; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and is substantially the same therewith and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line; and
the pair of selection gate transistors have substantially the same structure, each of the pair of transistors has a portion in which the impurity concentration of the channel region thereof is different in a gate length direction at a depth equal from the boundary between the semiconductor substrate and the gate insulation film, and the concentration distribution of impurity of the channel region of each transistor is different from that of the channel region of the memory cell.
According to a further aspect of the present invention, there is provided a non-volatile semiconductor memory device, comprising:
a plurality of memory cell units comprising at least one memory cell formed on a semiconductor substrate through a gate insulation film and having a laminated gate structure of a charge accumulation layer and a control gate layer; and
a plurality of selection gate transistor each having a gate electrode formed through a gate insulation film that is formed simultaneously with the gate insulation film of the memory cell and is substantially the same therewith and a source/drain diffusion layer one of which is connected to each memory cell unit and the other of which is electrically connected to a bit line or a source line,
wherein the plurality of selection gate transistors have a pair of selection gate transistors disposed in confrontation with each other across a contact portion connected to the bit line or to the source line and having substantially the same structure; and
the impurity concentration of the source diffusion layer of each of the pair of selection gate transistors is different from that of the drain diffusion layer thereof at a depth equal from the boundary between the semiconductor substrate and the gate insulation film as well as the effective impurity concentration of the source diffusion layer or the drain diffusion layer, which is connected to the bit line or the source line, of each selection gate transistor is lower than that the source/drain diffusion layer of the memory cell.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming the first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming an impurity doping mask having apertures corresponding to only the channel regions of the selection gate transistors on the semiconductor substrate; and
doping a first conductive type impurity in the semiconductor substrate through the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming a gate insulation film on the semiconductor substrate;
forming a part of gate electrodes on the gate insulation film;
forming element isolation regions on the surface layer portion of the semiconductor substrate in self-alignment using the part of gate electrodes as a mask;
forming an impurity doping mask having apertures corresponding to only the channel regions the selection gate transistors on the semiconductor substrate; and
doping a first conductive type impurity in the semiconductor substrate via the part of the gate electrodes through the mask.
According to a further aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, comprising:
forming first conductive type channel regions of a memory cell and selection gate transistors on the surface of a semiconductor substrate;
forming a gate insulation film on the semiconductor substrate;
forming a part of gate electrodes on the gate insulation film;
forming element isolation regions on the surface layer portion of the semiconductor substrate in self-alignment using the part of the gate electrodes as a mask;
forming an impurity doping mask having apertures corresponding to the channel regions the selection gate transistors and to the element isolation region of a transistor constituting the peripheral circuit of memory cell units; and
doping a first conductive type impurity in the semiconductor substrate via the part of the gate electrodes through the mask.